1. Field of the Invention
The present invention relates to a semiconductor storage device such as an SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), or a like and a method for remedying defects of memory cells therein, and more particularly to a semiconductor storage device and a method for remedying defects of memory cells by replacing a column or a row of memory cells containing a defective memory cell with a column or row of redundancy memory cells.
The present application claims priority of Japanese Patent Application No. 2001-368934 filed on Dec. 3, 2001, which is hereby incorporated by reference.
2. Description of the Related Art
Since a demand memory capacity of a semiconductor storage device tends to increase year by year, as a result, requiring its chip area to be made larger and its pattern to be scaled down more, complete eradication of a defective memory cell being unable to provide functions of normal writing and reading of data in one semiconductor becomes difficult. To solve this problem, a defective memory cell is remedied conventionally by mounting a column and a row each being made up of excessive memory cells (that is, redundant memory cells) to provide more memory capacity than needed in a semiconductor storage device and by replacing a column or a row containing defective memory cells with the column or row containing the redundant memory cells during a probe test for checking electrical characters or a like. This can achieve improvement of yields in semiconductor storage device products.
FIG. 11 is a schematic block diagram showing an example of configurations of a conventional semiconductor storage device in which memory cells are remedied by the method as described above. FIG. 12 is a circuit diagram showing an example of configurations of a column redundant decoder making up the conventional semiconductor storage device. The conventional semiconductor storage device of the example, as shown in FIG. 11, is made up of, for example, a DRAM, which has a memory cell array 1, a column decoder group 2, a column redundant decoder group 3, a row decoder group 4, a row redundant decoder group 5, a controller 6, an internal address generating circuit 7, and an input/output circuit 8. Moreover, the conventional semiconductor storage device of the example is provided, in addition to components described above, though not shown, with a sense amplifier to detect data signal read to a bit line from a memory cell and to amplify the detected data signal, an internal voltage generating circuit to generate an internal voltage to be fed to an internal circuit, or a like, all of which are mounted on one semiconductor chip by using known semiconductor manufacturing technology.
The memory cell array 1 is made up of a normal memory cell area 1a and redundant memory cell areas 1b and 1c. In the normal memory cell area 1a, a plurality of normal memory cells is arranged in a matrix form. The normal memory cells are mounted in a manner that a number of the normal memory cells that corresponds to a set storage capacity is provided in which data can be written and read when the memory cells are normal, that is, when the memory cells have no defects. In the redundant memory cell area 1b is arranged a plurality of columns of redundant memory cells (for example, ten columns) in a row direction at specified intervals, a number of which is same as those of normal memory cells making up a column (normal memory cell column) of a plurality of normal memory cells arranged at specified intervals in a row direction in the normal memory cell area 1a. In the redundant memory cell area 1c is arranged a plurality of rows of redundant memory cells (for example, ten rows) in a column direction at specified intervals, a number of which is same as those of normal memory cells making up the row (normal memory cell row) having a plurality of normal memory cells arranged at specified intervals in a column direction in the normal memory cell area 1a. 
The column decoder group 2 has a plurality of column decoders adapted to output, under control of the controller 6, a plurality of column normal selecting signals used to put a bit line being wired to each of corresponding columns having normal memory cells in the normal memory cell area 1a into a selected state, based on internal address signals A0 to AK each being made up of k bits (“k” is a natural number) fed from the internal address generating circuit 7. The column redundant decoder group 3 has “m”—pieces (“m” is a natural number) of column redundant decoders 91 to 9m each being mounted so as to correspond to each of “m” pieces of the redundant memory cells making up the redundant memory cell area 1b. Each of the column redundant decoders 91 to 9m outputs each of m-pieces of column redundant selecting signals CRS1 to CRSm used to put a bit line wired to each of corresponding columns of normal memory cells into a selected state, based on a test signal TEST, a pre-charging signal /PREc, a reset signal /RESETc, all being fed from the controller 6, and on the internal address signals A0 to AK described above. The test signal TEST is set to be at a high level while the probe test is conducted and to be at a low level when the semiconductor storage device of the example is used in a normal manner. The pre-charging signal /PREc is active low and is used to pre-charge a second input terminal of a column redundant selecting signal output circuit 12 (FIG. 12) making up each of the column redundant decoders 91 to 9m so that the above second input terminal is put into a high-level state. The reset signal /RESETc is active low and is used to reset a state of each of column redundant decoders 91 to 9m.
The row decoder group 4 has a plurality of row decoders adapted to output, under control of the controller 6, a plurality of row normal selecting signals used to put a word line being wired to each of corresponding rows of normal memory cells in the normal memory cell area 1a into a selected state, based on internal address signals A0 to AK. The row redundant decoder group 5 is provided with n-pieces (“n” is a natural number) of the row redundant decoders 101 to 10n (not shown) mounted so as to correspond to n-pieces rows of redundant memory cells making up the redundant memory cell area 1c. Each of the row redundant decoders 101 to 10n (not shown) outputs each of m-pieces of row redundant selecting signals RRS1 to RRSn used to put a word line wired to each of corresponding rows of normal memory cells into a selected state, based on a test signal TEST, pre-charging signal /PRER, reset signal /RESETR, all being fed from the controller 6, and on the internal address signals A0 to AK described above. The pre-charging signal/PRER is active low and is used to pre-charge a second input terminal of a row redundant selecting signal outputting circuit (not shown) making up each of the row redundant decoders 101 to 10n (not shown) so that the above second input terminal is put into a high-level state. The reset signal /RESETR is low active and is used to reset a state of each of the row redundant decoders 101 to 10n (not shown) The controller 6, when a level of a clock enable signal CKE fed from an outside is changed from a high to a low, decodes a command represented by a combination of a chip select signal /CS, a write enable signal /WE, a row address strobe signal /RAS, and a column address strobe signal /CAS, all being fed in synchronization with a clock CLK fed from the outside and controls each of components. All of the chip select signal /CS, write enable signal /WE, row address strobe signal /RAS, and column address strobe signal /CAS are low active. For example, the controller 6, based on the decoded command, feeds a generating timing signal used to determine timing for generation of internal addresses in the internal address generating circuit 7 to the internal address generating circuit 7 and/or a column decoder activating signal to used to activate a plurality of column decoders making up the column decoder group 2 to the column decoder group 2. Moreover, the controller 6 generates the test signal TEST, pre-charging signal /PREc, and reset signal /RESETc and feeds them to the column redundant decoder group 3, and also generates the test signal TEST, pre-charging signal /PRER and reset signal /RESETR to the row redundant decoder group 5. The internal address generating circuit 7, based on an address signal AD made up of a plurality of bits fed from an outside, generates internal address signals A0 to AK of k bits and feeds them to each components of the semiconductor storage device. The input/output circuit 8 chiefly includes a data amplifier (not shown) used to amplify data detected and amplified by a sense amplifier (not shown) under control of the controller 6 and fed through an input/output line (not shown) and a write amplifier (not shown) used to amplify, under control of the controller 6, data fed from an outside.
Next, configurations of the column redundant decoder 91 making up the column redundant decoder group 3 will be described by referring to FIG. 12. The column redundant decoder 91 of the example has an address decoder 11, the column redundant selecting signal output circuit 12, an OR gate 13, p-channel MOS (Metal Oxide Semiconductor) transistors 141 and 142, n-channel MOS transistors 151 to 153, 160 to 16k, and 170 to 17k, exclusive OR gates 180 to 18k, enable-terminal-attached delay flip-flops (DFFs) 19 and 200 to 20k, an enable fuse 21, address fuses 220 to 22k, and an inverter 23.
The address decoder 11, when a high level test signal TEST is fed to its first input terminal during the above probe test and address signals A0, A1, . . . , Ak each being set to represent an address of a corresponding column containing redundant memory cells in the redundant memory cell area 1b in the memory cell array 1 are fed to its other input terminals, outputs a high-level column redundant selecting signal TCRS, during the probe test. The column redundant selecting signal output circuit 12, when a low-level test signal TEST is fed to its first input terminal when the semiconductor storage device is used in an ordinary manner and when a high-level selecting confirming signal SCFM1 is fed after its second input terminal has been pre-charged by the pre-charging signal /PREc so as to be put into a high-level state, outputs a high-level column redundant selecting signal NCRS1 being used when the semiconductor storage device is used in an ordinary manner. The selecting confirming signal SCFM1 goes high when the address signals A0, A1, . . . , Ak each being assigned to each of the columns of normal memory cells are fed in the case where a corresponding column of redundant memory cells in the redundant memory cell area 1b in the memory cell array 1 is replaced with a column of normal memory cells and when selection of the column containing redundant memory cells is confirmed. The OR gate 13 operates to OR the column redundant selecting signal TCRS1 being used during the probe test with the column redundant selecting signal NCRS1 and outputs a result from the OR calculation as a column redundant selecting signal CRS1.
To a source of the MOS transistor 141 is applied a supply voltage VDD and to its gate is fed a pre-charging signal /PREc and its drain is connected to each of drains of the MOS transistors 152, 160 to 16k. To a source of the MOS transistor 142 is applied a supply voltage VDD and to a gate of the MOS transistor 142 and commonly to a gate of the MOS transistor 151 is fed a pre-charging signal /PREc and a drain of the MOS transistor 142 is connected to a drain of the MOS transistor 151 and each of drains of the MOS transistors 152 and MOS transistors 160 to 16k. A source of the MOS transistor 151 is connected to a ground. The MOS transistors 142 and 151 make up the inverter 23. A gate of the MOS transistor 152 is connected to an output terminal Q of the DFF 19. Each gate of the MOS transistors 160 to 16k is connected to each of output terminals of corresponding exclusive OR gates.
To each of first input terminals of the exclusive OR gates 180 to 18k is fed each of corresponding address signals A0 to Ak and each of second input terminals of the exclusive OR gates 180 to 18k is connected to each of output terminals Q of corresponding DFFs 200 to 20k. An input terminal D of the DFF 19 is connected to a connecting point between one end of the enable fuse 21 and a drain of the MOS transistor 153 and a reset signal /RESETc is fed to an enable terminal EN of the DFF 19. An input terminal D of each of the DFFs 200 to 20k is connected to a connecting point between one end of corresponding address fuses 220 to 22k and each drain of the corresponding MOS transistors 170 to 17k and a reset signal /RESETc is fed to each of the enable terminals EN. To each of other terminals of the address fuses 220 to 22k is applied a supply voltage VDD. The inverter 23 reverses the reset signal /RESETc and feeds the reversed signal to each of gates of the MOS transistors 153, and 170 to 17k. Each of sources of the MOS transistors 153, and 170 to 17k is connected to a ground.
Moreover, configurations of the column redundant decoders 92 to 9m and the row redundant decoders 101 to 10n making up the row redundant decoder group 5 are almost same as those of the column redundant decoder 91 except that input and output signals or a number of each of various components is different and their descriptions are omitted accordingly.
In the semiconductor storage device having configurations described above, defective memory cells are replaced with redundant memory cells. Examples of the defective memory cells are ones that have data holding time being shorter than designated by specifications or have poor electric contact. A rate of occurrence of defective memory cells having data holding time being shorter than designated by specifications becomes higher in an accelerated manner when a temperature becomes higher while a rate of occurrence of defective memory cells having poor electric contact becomes higher in an accelerated manner when the temperature becomes lower. As patterns in the semiconductor storage device are scaled down more, such the defective memory cells occur more to a degree that cannot be ignored. To solve this problem, in recent years, a probe test is carried out twice separately, that is, when the temperature is high and low, so that remedy of defective memory cells having data holding time being shorter than designated by specifications and remedy of defective cells having poor electric contact are independently performed in a separate manner.
Therefore, when m=n=10, that is, if a number of columns of redundant memory cells is ten and if a number of rows of redundant memory cells is ten, seven columns out of ten columns of redundant memory cells are assigned to remedy defective memory cells judged to be defective in tests conducted at high temperatures and remaining three columns of redundant memory cells are assigned to remedy defective memory cells having been judged to be defective in the test conducted at low temperatures. By the same way as above, some rows of redundant memory cells are assigned to remedy defective memory cells having been judged to be defective in the test conducted at high temperatures and remaining some rows of redundant memory cells are assigned to remedy defective memory cells having been judged to be defective in the test conducted at low temperatures. Moreover, in an initial state, in the column redundant decoders 91 to 9m making up the column redundant decoder group 3 and in the row redundant decoders 101 to 10n (not shown) making up the row redundant decoder group 5, the enable fuse 21 and address fuses 220 to 22k are still in a state in which they have not been removed.
Next, processes of the probe test and operations of the semiconductor storage device having configurations described above will be described by referring to a flowchart shown in FIG. 13. First, a test is conducted on the semiconductor storage device to check electrical characteristics by placing its semiconductor wafer on which a lot of the semiconductor storage devices are formed under high temperatures at which defective memory cells having data holding time being shorter than designated by specifications tends to occur more and by supplying specified information about the test to the normal memory cell area 1a in the memory cell array 1 (Step SA1). In the above test for checking electrical characteristics, for example, direct current tests and/or alternating current tests are conducted by using a wafer prober, and by putting a probe thereof into contact with a pad of each of the semiconductor chips on the semiconductor wafer having already undergone wafer processing.
Next, same tests for checking electrical characteristics of the redundant memory cells as conducted in Step SA1 are done by feeding specified information about tests to the redundant memory cell areas 1b and 1c in the memory cell array 1 while the semiconductor wafer is being placed under high temperatures as above (Step SA2). Here, operations of the column redundant decoder 91 performed during the test for checking electrical characteristics will be described by referring to the circuit diagram shown in FIG. 12 and the timing chart shown in FIG. 14. First, as shown in FIG. 14 (1), after having set a TEST signal to be at a high level and then as shown in FIG. 14 (2), a reset signal /RESETc is set to be at a low level for a specified period of time. This causes the inverter 23 to reverse the reset signal /RESETc and to feed it to a gate of each of the MOS transistors 153 and 170 to 17k and, as a result, each of the MOS transistors 153 and 170 to 17k is turned ON. In this case, the enable fuse 21 and address fuses 220 to 22k are still in a state in which they have not been removed. Therefore, to the input terminal D of the DFF 19 and 200 to 20k is applied a supply voltage VDD, that is, a high-level voltage. As a result, each of the DFFs 19 and 200 to 20k having been put in an enable state by a low-level reset signal /RESETc captures and holds a high-level voltage obtained when the enable fuse 21 and address fuses 220 to 22k are still in a state in which they have not been removed. That is, the DFF 19 outputs a high-level signal and feeds it to the gate of the MOS transistor 152. On the other hand, each of the DFF 200 to 20k outputs a high-level signal and feeds it to a second terminal of each of corresponding exclusive OR gates 180 to 18k.
Next, while the pre-charging signal /PREc is kept at a high level as shown in FIG. 14 (3), address signals A0, A1, . . . , Ak each being assigned to each of the columns of normal memory cells, as an address, are fed to each of the columns of redundant memory cells corresponding to the column redundant decoder 91 as shown in FIG. 14 (4). This causes the address decoder 11 to output a high-level column redundant selecting signal TCRS1 as shown in FIG. 14 (5). On the other hand, since a high-level test signal TEST was fed to a first input terminal of the column redundant selecting signal output circuit 12, a low-level column redundant selecting signal NCRS1 has been output as shown in FIG. 14 (6). Therefore, the OR gate 13, as shown in FIG. 14 (7), outputs a high-level column redundant selecting signal CRS1. As a result, since a sense amplifier (not shown) connected to the bit line being wired to the corresponding redundant memory cell column is put in a selected state, the test for checking electrical characteristics of a plurality of redundant memory cells making up the redundant memory cell column is made possible. Moreover, diagonally shaded areas in address signals A0 to Ak shown in FIG. 14 (4) represent that the signals to be used may be at a high level or at a low level.
Then, trimming data is created which is used to perform a trimming, by using a laser, the enable fuse 21 and address fuses 200 to 22k, based on a result from the test on normal memory cells conducted in Step SA1 and a result from the test on redundant cells conducted in Step SA2, in the column redundant decoders 91 to 9m making up the column redundant decoder group 3 and in the row redundant decoders 101 to 10n (not shown) making up the row redundant decoder group 5 (Step SA3). That is, the trimming data is created which is used to replace normal memory cell columns containing memory cells judged to be defective by the test on normal memory cells conducted at high temperatures, out of normal memory cell columns making up the normal memory cell area 1a, with any one of seven pieces of redundant memory cell columns assigned to remedy memory cells judged to be defective by the test conducted at high temperatures, out of ten pieces of the redundant memory cell columns making up the redundant memory cell area 1b, and judged, as a result from the tests on the redundant memory cells, to have contained no defective memory cells. Similarly, trimming data is created which is used to replace normal memory cell rows containing memory cells judged to be defective by the test conducted at high temperatures with redundant memory cell rows assigned in advance.
Next, a trimming is performed to cut any one of the enable fuse 21 and address fuses 200 to 22k of the column redundant decoder 91 to 9m and the row redundant decoders 101 to 10n (not shown) by using a laser, based on the trimming data produced by the procedure in Step SA3 (Step SA4). FIG. 15 shows one example of the result from the trimming process. In the example shown in FIG. 15, the enable fuse 21 and the address fuses 221 and 222 out of the address fuses 220 to 22k have been removed in the column redundant decoder 91.
Next, tests for checking electric characteristics are conducted by placing the semiconductor wafer under low temperatures at which defective memory cells having poor electric contact tend to occur more and by feeding specified information about the test to the normal memory cell area 1a in the memory cell array 1 (Step SA5). Then, same tests for checking electric characteristics as in Step SA5 are conducted by placing the semiconductor wafer under the low temperature and feeding specified information about the test to the redundant memory cell areas 1b and 1c in the memory cell array 1 (Step SA6). Moreover, operations of the column redundant decoder 91 performed when tests for checking electric characteristics are conducted are the same as those explained by referring to the timing chart shown in FIG. 14 and their descriptions are omitted.
Next, trimming data is created which is used to perform a trimming on the enable fuse 21 and address fuses 200 to 22k of the column redundant decoders 91 to 9m and the row redundant decoders 101 to 10n (not shown) by using a laser, based on a result from tests on normal memory cells conducted in Step SA5 and based on a result from tests on redundant memory cells conducted in Step SA6 (Step SA7). That is, the trimming data is created which is used to replace normal memory cell columns containing memory cells having been judged to be defective by the test on normal memory cells conducted at low temperatures, out of normal memory cell columns making up the normal memory cell area 1a, with any one of three pieces of redundant memory cell columns assigned to remedy memory cells having been judged to be defective by the test conducted at low temperatures, out of ten pieces of the redundant memory cell columns making up the redundant memory cell area 1b, and having been judged, as a result from the tests on the redundant memory cells, to contain no defective memory cells. Similarly, trimming data is created which is used to replace normal memory cell rows containing memory cells judged to be defective by the test conducted at low temperatures with redundant memory rows assigned in advance.
Next, after having performed the trimming process to cut any one of the enable fuse 21 and address fuses 200 to 22k of the column redundant decoder 91 to 9m and the row redundant decoders 101 to 10n (not shown) by using the laser, based on trimming data produced by the procedure in Step SA7 (Step SA8), a series of the processes is terminated.
In the above configurations, seven pieces of columns out of the redundant memory cell columns are assigned for remedying memory cells judged to be defective in the tests conducted at high temperatures and remaining three pieces of the redundant memory cell columns are assigned for remedying memory cells judged to be defective in the tests conducted at low temperatures and such the assignment is determined by including manufacturing conditions of the semiconductor wafer and statistical elements and experimental elements related to the manufacturing. However, the conventional method for remedying defective memory cells described above has a problem in that, since occurrence of defective memory cells varies depending on specifications of the semiconductor storage device, a number of a large number of semiconductor wafers, and a number of semiconductor chips making up the semiconductor wafers, the above method in which redundant memory cell columns and rows are assigned in advance cannot provide an optimum method for remedying defective memory cells. That is, in the example of the conventional method, if, out of seven pieces of columns of redundant memory cells assigned to remedy memory cells judged to be defective in tests conducted at high temperatures, only three pieces of the columns are replaced in an actual operation, the remaining four pieces of columns remains in an unused state despite of normal operations of the memory cells, thus causing a shortcoming that efficiency of using redundant memory cells is low. Additionally, if columns of redundant memory cells exceeding three pieces of columns assigned to remedy memory cells judged to be defective in tests conducted at low temperatures, for example, four pieces of the columns are required to remedy memory cells judged to be defective in the tests conducted at low temperatures, neither the optimum assignment of memory cells nor remedy itself of defective memory cells can be achieved. As a result, the semiconductor chip itself has to be discarded as a defective, causing a decrease in yields of the semiconductor storage device products. In a current state where occurrence of defective memory cells tends to increase more as patterns for the semiconductor storage device are scaled down more, such the case as described above is thought to more often occur in the future.
In order to increase the efficiency of using the redundant memory cells, another possible method is not to assign, in advance, the redundant memory cell columns and the redundant memory cell rows for remedying memory cells judged to be defective in tests conducted at high temperatures and judged to be defective in tests conducted at low temperatures. However, if the redundant memory cell columns and rows are not to be assigned, since, in the second time test (process in Step SA6) on the redundant memory cells, since the redundant memory cell columns and rows, even if they have been replaced, are judged to be a “PASS” (that is, as being usable) as a result from the test, it is impossible to judge whether or not the redundant memory cell columns and rows have been already replaced.